1. Field of Invention
The present invention relates to a structure for preventing leakage of a semiconductor device. More particularly, the present invention relates to a structure for prevention of a parasitic transistor, which exists in a region including at least one semiconductor device, from causing leakage of the semiconductor device.
2. Description of Related Art
Typically, integrated circuits (ICs) operate at various operating voltages. Therefore, transistors in these ICs must withstand certain voltage thresholds. For example, transistors with gate lengths of less than 0.25 μm typically operate at less than 2.5 volts, while transistors with longer gate length (>0.3 μm) may operate at well over 3 volts. In certain high voltage applications such as power supplies and hard-disk controllers, even higher operating voltage ranging from 6 volts to 35 volts may be required.
There is at least one insulation layer, which is used to insulate the conductive lines and the active region above the high voltage devices, however, the high operating voltage also affects the active region. If the conductive line crosses over two separated doped regions of the active region, a parasitic transistor might be constructed. The parasitic transistor will cause leakage of the doped regions, and the performance of the devices containing the doped regions decreases. Hereby a pair of N-type high voltage transistors is used as an example to describe the reasons for forming parasitic transistor. The parasitic transistor also occurs between a pair of P-type high voltage transistors, and between a transistor and a doped region.
FIG. 1 is a schematic, cross-sectional view of a pair of the traditional N-type high voltage transistors. P-type wells 102, 104, 106 and N-type wells 108, 110 are located on a substrate 100. The shallow trench isolation (STI) structures 112, 114, 116, 118, 120 and 122 are respectively located in the P-type well 102, between P-type well 102 and N-type well 108, in N-type well 108, between N-type well 108 and P-type well 104, between P-type well 104 and N-type well 110, in the N-type well 110, and in the P-type well 106.
With further reference to FIG. 1, high voltage transistors 10 and 20 are formed on the substrate 100. The transistor 10 has a source 12, a drain 14 and a gate 16. The source 12 is located in the P-type well 102 and at the right side of the STI 112. The drain 14 is located in the N-type well 108 and between STI 114 and 116. The gate 16 is located on the surface of the substrate 100 and crosses over P-type well 102, N-type well 108 and STI 114. The transistor 20 has a source 22, a drain 24 and a gate 26. The source 22 is located in the P-type well 106 and at the left side of the STI 120. The drain 24 is located in the N-type well 110 and between STI 118 and 120. The gate 26 is located on the surface of the substrate 100 and crosses over P-type well 106, N-type well 110 and STI 120. A guard ring 124 is located in the substrate 100 and surrounds the structures disclosed above. An insulation layer 126 blankets all features located on the substrate 100 and a conductive line 128 is located on the insulation layer 126. The conductive line 128 crosses over the position above the P-type well 104. Besides, another conductive line (not shown) also can be formed on the conductive line 128, and the two conductive lines are isolated by another insulation layer (not shown).
FIG. 2 is a schematic, top view of the device in FIG. 1. The structures inside the circle 140 consist a parasitic transistor, in which the conductive line 128 is a parasitic gate, the drain 14 of transistor 10 and N-type well 104 are one of the parasitic source/drain, the drain 24 of transistor 20 and N-type well 110 are another parasitic source/drain, and the P-type well 104 is the parasitic channel region. The parasitic transistor could be turned on while a current flows through the conductive line 128 and the leakage form the transistors 10 and 20 will occur.
The parasitic transistor does not only exist between two high voltage transistors, but also exist when a conductive line crosses over a region between a high voltage transistor and the guard ring. FIG. 3 is a schematic, top view of a high voltage transistor. A N(or P)-type well 34 is located between a source/drain 30 and a guard ring 32. When a conductive line 36 crosses over the N(or P)-type well 34, the structures inside the circle 340, the conductive line 36, the source/drain 30 and the guard ring 32, consist a parasitic transistor. Therefore, if the conductive lines, located at the upper layer, cross over the N/P-type well or active region on the substrate, parasitic transistors may be constructed.
The parasitic transistor will be turned on when a current flows through the conductive line. The performance of the high voltage transistor decreases due to the leakage caused by switching on of the parasitic transistor. Therefore, avoiding the effect of the parasitic transistor is an important subject.